A Platform for Combining Deductive with Algorithmic Verification

We describe a computer-aided veriication system which combines deductive with algorithmic (model-checking) veriication methods. The system, called tlv (for temporal veriication system), is constructed as an additional layer superimposed on top of the cmu smv system, and can verify nite-state systems relative to linear temporal logic (ltl) as well as ctl speciications. The systems to be veriied can be either hardware circuits written in the smv design language or nite-state reactive programs written in a simple programming language (spl). The paper presents a common computational model which can support these two types of applications and a high-level interactive language tlv-Basic, in which temporal veriication rules, proofs, and complex assertions can be written. We illustrate the eeciency and generality gained by combining deductive with algorithmic techniques on several examples, culminating in veriication of fragments of the Futurebus+ system. In the analysis of the Futurebus+ system , we even managed to detect a bug that was not discovered in a previous model-checking analysis of this system.